Conventional power on reset circuitry is used to ensure that memory and logic circuits are in known states at power up. However, the use of multiple power rails in some designs complicates power on reset techniques. Take, for example, a system that has three power rails—MX, CX, PX. When the system is powered up, the MX power rail comes up first, followed by CX, and lastly PX.
Today's complex systems on chip (SoCs) have started using power generation structures such as power multiplexors (muxes) that can provide the option of flipping the power supply of downstream logic to one supply during normal operation and another supply for special conditions such as high performance modes or deep sleep modes. For example, one system may use power muxes to provide power to a retention rail of retention flip-flops. In normal operational mode, power mux supplies VDD_CX and in deep sleep mode, when CX is collapsed, the mux switches to VDD_MX in order to keep the data retained in flops.
Continuing with the example, a controller that controls the signals to the power mux operates on the MX power domain, but there is no reset generated in the system when only MX has come up but the other power domains have not yet come up. Reset is typically generated much later once other power rails are up. However, if the controller is not reset at the moment when MX turns on or if the control signals to the power mux are not clamped to a proper value when MX turns up, the control signals could cause the power mux to go to an unknown state, potentially causing a short between VDD_CX and VDD_MX.
Thus, there is a need in the art for a circuit that can create stable clamp and reset signals at the start from within the SoC that will allow known signals to be fed into the power mux during a period when the first power domain has come up but other power domains have not yet come up.